PIC18F45J11-I/ML【PDF 170/228 页】IC PIC MCU FLASH 32K 2V 44-QFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3862

166页 167页 168页 169页 [170页]171页 172页 173页 174页

PIC18F46J11 FAMILY

DS39932D-page 46

2011 Microchip Technology Inc.

3.5

Effects of Power-Managed Modes

on Various Clock Sources

When the PRI_IDLE mode is selected, the designated

primary

oscillator

continues

run

without

interruption. In secondary clock modes (SEC_RUN

and SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

In internal oscillator modes (RC_RUN and RC_IDLE),

the internal oscillator block provides the device clock

source. The 31 kHz INTRC output can be used directly

to provide the clock and may be enabled to support

various

special

features

regardless

the

power-managed mode (see Section 26.2 “Watchdog

Timer (WDT)”

, Section 26.4 “Two-Speed Start-up”

and Section 26.5 “Fail-Safe Clock Monitor” for more

information on WDT, FSCM and Two-Speed Start-up).

The INTOSC output at 8 MHz may be used directly to

clock the device or may be divided down by the

postscaler. The INTOSC output is disabled if the clock

is provided directly from the INTRC output.

If Sleep mode is selected, all clock sources, which are

no longer required, are stopped. Since all the transistor

switching currents have been stopped, Sleep mode

achieves the lowest current consumption of the device

(only leakage currents) outside of Deep Sleep mode.

Enabling any on-chip feature that will operate during

Sleep mode increases the current consumed during

Sleep mode. The INTRC is required to support WDT

operation. The Timer1 oscillator may be operating to

support an RTC. Other features may be operating that

do not require a device clock source (i.e., MSSP slave,

PMP, INTx pins, etc.). Peripherals that may add

significant

current

consumption

are

listed

Section 29.2 “DC Characteristics: Power-Down and

Supply Current PIC18F46J11 Family (Industrial)”

3.6

Power-up Delays

Power-up delays are controlled by two timers so that no

external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply is stable under

normal circumstances and the primary clock is operat-

ing and stable. For additional information on power-up

delays, see Section 5.6 “Power-up Timer (PWRT)”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 29-15).

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crystal oscillator is stable (HS mode). The OST does

this by counting 1024 oscillator cycles before allowing

the oscillator to clock the device.

There is a delay of interval, TCSD (parameter 38,

Table 29-15), following POR, while the controller

becomes ready to execute instructions. This delay runs

concurrently with any other delays. This may be the only

delay that occurs when any of the internal oscillator or

EC modes are used as the primary clock source.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式